Indium phosphide (InP) also called indium phosphorus is a group III-V compound semiconductor material composed of indium (In) of group III (group 13) and phosphorus (P) of group V (group 15). As the semiconductor material, the InP has characteristics of a band gap of 1.35 eV, and an electron mobility up to 500 cm2N·s, which is a higher electron mobility than other general semiconductor materials such as silicon and gallium arsenide. Further, the InP is characterized in that a stable crystal structure under normal temperature and pressure is a cubic zinc blende structure, and its lattice constant is larger than that of a compound semiconductor such as gallium arsenide (GaAs) and gallium phosphide (GaP).
Single crystal InP has a higher electron mobility than silicon (Si) and the like, and it is, therefore, used as a material for high-speed electronic devices utilizing it. Further, the single crystal InP has a larger lattice constant than that of gallium arsenide (GaAs) or gallium phosphide (GaP) and can decrease a lattice mismatch rate when used as a substrate for heteroepitaxial growth of a ternary mixed crystal such as InGaAs and quaternary mixed crystal such as InGaAsP. Therefore, the single crystal InP is used for various optical communication devices such as semiconductor lasers, optical modulators, optical amplifiers, optical waveguides, light emitting diodes, and light receiving elements, which form those mixed crystal compounds as a laminated structure, and is used as a substrate for compound optical integrated circuits thereof.
The substrate for forming the various devices as described above are produced through the following steps, for example. First, a single crystal InP ingot is cut into thin plates (wafers) in a predetermined crystal orientation (a slicing step). Both surfaces of each wafer are then ground and coarsely polished or rubbed against flat surfaces such as iron or glass plates with an abrasive (a lapping step) to reduce a variation of wafer thickness. The surfaces of the wafer surface is then mirror-polished (a polishing step) to obtain a wafer with high flatness. The wafer is then washed (a rinse step), and inspected for the presence or absence of defects or dusts on the wafer (an inspection step). To obtain a wafer with high flatness, the mirror-polishing (polishing) step is particularly important.
Recently, the flatness of the wafer is focused on various surface roughness such as Ra (arithmetic mean roughness), Rz (maximum height roughness) and Rq (root mean square roughness) which are generally used in the prior art, and evaluation indices such as a whole or local thickness variation of the wafer (TTV; Total Thickness Variation, LTV; Local Thickness Variation), as well as edge roll off (ERO; Edge-Roll-Off) indicating a so-called “surface sagging” near an edge of the wafer surface. In general, a semiconductor wafer or the like whose surface has been mirror-polished has a surface shape in which flatness is deteriorated near an edge of the wafer, resulting in “surface sagging”, because of the characteristics of the polishing step.
With the miniaturization of semiconductor devices, a demand for resolution of an exposure apparatus used for forming the device has become severer. To achieve higher resolution, it is necessary to shorten a wavelength of an exposure light source, but a depth of focus of an optical system of the exposure apparatus becomes shallower accordingly. Therefore, in the recent device processing technique which has been miniaturized, the surface of the wafer forming the device has also been required to be sufficiently flat because the depth of focus of the optical system of the exposure apparatus has been shallower. However, the use of the wafer with larger ERO as described above results in poor performance of the device produced near the edge of the wafer, leading to a deterioration of a final production yield and an increase in product cost.
Therefore, in order to maximize an effective device-forming region on the wafer and suppress variations in the performance between devices to be formed, it is important to obtain a wafer with reduced ERO. It is believed that the generation of ERO is caused by a difference in a process parameter related to polishing between a central portion and an edge portion of the wafer, such as a difference in a relative moving speed of the wafer to a polishing pad between the vicinity of the central portion of the wafer and the vicinity of the edge portion of wafer during the mirror-polishing process of the wafer. Therefore, to reduce ERO, it is necessary to consider a polishing method closely related to the reduction of ERO.
For the method for polishing the wafer, the following prior arts are known. Patent Document 1 describes a method for polishing a gallium nitride (GaN) wafer, in which the wafer is polished with a soft material having a Vickers hardness Hv in a range of 50≤Hv≤2800. Patent Document 2 discloses that polishing is performed by dividing a polishing process into two stages and setting different polishing conditions at each stage. Although not related to the polishing method, each of Patent Document 3 and Non-Patent Document 1 discloses that a wafer is evaluated by an evaluation value of a Roll-off amount (ROA) which quantifies a degree of ERO, as a parameter indicating flatness near the edge portion of the wafer. Patent Document 3 also describes an example in which an ROA value of about 10 nm is achieved in a silicon wafer.
However, Patent Document 1 is an art relating to GaN wafers, and Patent Documents 2 and 3 relate to Si wafers, which are not related to the InP wafer targeted by the present invention. Both GaN and Si single crystals are rigid materials each having a Young's modulus of from about 180 to 200 GPa, whereas the InP has a Young's modulus of about 60 GPa and is a soft and brittle material as a semiconductor material. Also, their chemical properties are quite different for each substance. Therefore, for the process of polishing in which an action of physical force and a type and process of chemical reaction greatly affect the result, the technical findings for other materials such as GaN and Si cannot be simply applied to the InP.
In general, the polishing of the InP wafer is carried out by placing the wafer on a rotating surface plate having a polishing pad on its surface and rotating the surface plate and the wafer while supplying a polishing solution having a predetermined composition, thereby gradually removing the elements on the surface of the wafer by, a mechanical or chemical action. As the composition of the polishing solution, a composition containing a combination of abrasive fine particles having a mechanical grinding action of the surface of the wafer such as colloidal silica and a chlorine compound having a chemical etching action, as described in Patent Document 4 or Patent Document 5, is conventionally known. Also, a method for flattening the surface of the InP wafer by a chemical etching action is conventionally known as described in Patent Document 6 or the like.
In these prior arts relating to polishing of the InP wafer, means and conditions for polishing are optimized from the viewpoints of TTV or undulation of the wafer, residual impurities and scratches, a polishing rate, a polishing efficiency and the like. However, in these prior arts there is no recognition of ERO which has been emphasized with recent miniaturization and there is no specific means effective for reducing ERO nor any technical teaching.
Non-patent document 2 mentions “roll-off” (which has the same meaning as ERO) for the InP single crystal wafer, and discloses that any optimum polishing composition is not well known for the InP and that prolonged polishing with a soft polishing cloth tends to increase the roll-off. However, even in this prior art there is only a slight vague teaching as described above, and any specific polishing composition and polishing conditions effective for reducing ERO are not clear. Furthermore, this prior art does not disclose any specific value of the roll-off value achieved.